Testing of physical microprocessors generally involves loading a known state into the processor, e.g., through the use of internal scan chains, running the processor for a predetermined number of cycles, and then downloading the state for comparison with a state predicted by software simulation of the processor. If the actual state matches the predicted state, then the microprocessor has passed the particular test.
In modern high performance microprocessors, there is often one clock controlling internal operations and a second clock controlling interface logic with external components such as communications buses. Since two clock sources control each signal, the state of the processor as a whole cannot always be predicted with absolute certainty. This makes it very difficult to accurately determine whether a particular processor chip functions as intended.
A strand is an execution pipeline within a microprocessor core. Some processors have only one strand per core, while others may have multiple strands per core. Having multiple strands per core provides faster context switching and improved performance. When the execution engine switches from one process to another process, it may change contexts from one execution pipeline to another. When a microprocessor boots up, it is necessary that each strand be “unparked” prior to the start of execution. A “strand unpark” signal is therefore sent to the processing core. In certain multi-strand processors, the CPU is booted upon receipt of a signal from an input pin. This resulted in indeterministic behavior due to multiple clocks. For reliable testing, it is important that the strand be unparked in a deterministic manner with respect to multiple clock signals. Some mechanism is therefore needed to resolve the indeterminism in booting and testing a chip having multiple clock domains.